1. Field of the Invention
This invention relates to an information processing device, and particularly to a partial multiplier selector for a multiplication circuit.
2. Description of the Prior Art
A multiplier device using the Booth Algorithm often divides the necessary multiplier into several partial multipliers, sequentially selects the partial multipliers and accumulates a plurality of partial products in order to save the hardware capacity. Conventionally, multiplexers have been used for such division and selection of multipliers, and the multiplication has been performed by sequentially activating the selection signal using a programmable controller.
FIG. 7 shows an example of a multiplier division/selection circuit using multiplexers. In this example, a 16 bit multiplier is divided into four partial multipliers and the partial multiplier data having a width of five bits are selected from four locations. The width of the partial multipliers are not four bits but five bits, because each divided partial multiplier must have one bit overlapping in the Booth Algorithm.
The reference numeral 701 indicates a multiplier register which stores 16 bits including a bit 0 located at the right end and a bit 15 located at the left end. The numeral 702 is a programmable controller, 703 is a multiplication start signal, 704 is a selection signal to select one of the bits 15 to 11 in the multiplier register 701, 705 is a reverse signal of the selection signal 704, 706 is a selection signal to select one of the bits 11 to 7 in the multiplier register 701, 707 is a reverse signal of the selection signal 706, 708 is a selection signal to select one of the bits 7 to 3 in the multiplier register 701, 709 is a reverse signal of the selection signal 708, 710 is a selection signal to select one of the bits 3 to 0 in the multiplier register 701 and a fixed value (=0), 711 is a reverse signal of the selection signal 710, 712 is a multiplexer which selects one of the bits 15, 11, 7 and 3 in the multiplier register 701, 713 is a multiplexer which selects one of the bits 14, 10, 6 and 2 in the multiplier register 701, 714 is a multiplexer which selects one of the bits 13, 9, 5 and 1 in the multiplier register 701, 715 is a multiplexer which selects one of the bits 12, 8, 4 and 0 in the multiplier register 701, 716 is a multiplexer which selects one of the bits 11, 7 and 3 in the multiplier register 701 and the fixed value, 717 is a Booth decoder to receive partial multipliers, 718 is a grounding component to provide the fixed value to the multiplexer 716, and 719 is a clock signal to operate the programmable controller 702.
The operation of the multiplier division/selection circuit in FIG. 7 is now described referring to the timing chart in FIG. 8. Firstly, a multiplier is stored in the multiplier register 701, and then the multiplication start signal 703 having a width of one clock is provided to the programmable controller 702 (801 in FIG. 8).
Synchronizing with this multiplication start signal 703, the selection signals 704 and 705 are issued by the programmable controller 702 (802). The remaining selection signals 706 to 711 are not activated and the selection signal 704 only becomes active for one clock. This activates the clocked inverter for bit 15 in the multiplexer 712 and the reversed value of the bit 15 in the multiplier register 701 is input to the Booth decoder 717.
Similarly, reversed values of the bits 14, 13, 12 and 11 in the multiplication register 701 are input from the multiplexers 713 to 716 to the Booth decoder 717 (803). The programmable controller 702 makes the selection signals 704 and 705 inactive in the next clock, and the selection signals 706 and 707 becomes active (804). These selection signals 706 and 707 cause the multiplexers 712 to 716 to provide the reversed values of the bits 11, 10, 9, 8 and 7 in the multiplier register 701 to the Booth decoder 717 (805).
In similar procedures, the programmable controller 702 issues the selection signals 708 and 709 and 710 and 711 with giving them intervals of one clock so that the reversed values of the bits 7 to 3 and 3 to 0 in the multiplier register 701 are sequentially input to the Booth decoder 717 (806, 807). The least significant bit of the five bits input to the Booth decoder 717 at the last must be fixed to zero in the Booth Algorithm, and the bits actually selected from the multiplier register 701 are only four (3 to 0).
A conventional multiplier device has used multiplexers for division and selection of partial multipliers as described above, and required so many programmable controllers and selection signal lines for selection of partial products, resulting in an enormous scale of hardware. Besides, if the multiplier device is to be realized on an LSI, complicated wiring from the multiplier register to multiplexers requires a large area for layout.